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Solve The Effect of PCB Layered Stacking on EMI Suppression
gesptechnologypcbJune 1, 2017 Blog 0 Comment310views

Power Bus

In the IC power supply pin near the appropriate placement of the proper capacity of the capacitor, IC output voltage can jump faster. However, the problem is not so far. Since the capacitor has a characteristic of a limited frequency response, this makes it impossible to generate the harmonic power required to drive the IC output in a full frequency band. Also, the transient voltage formed on the power supply bus creates a voltage drop across the inductor at both ends of the decoupling path. These transient voltages are the primary standard mode of EMI sources. How should we solve these problems?

For the ICs on our circuit boards, We can see the power supply layer around the IC as a first high-frequency capacitor that collects the amount of energy that is leaking from discrete capacitors that provide high-frequency energy for clean output. Also, the excellent power supply layer inductance is small, so the inductance of the synthesis of the transient signal is too tiny, thereby reducing the standard mode EMI.

Of course, the connection between the power supply layer and the IC power supply pin must be as short as possible because the rising edge of the digital signal is faster and faster, and it is best to connect directly to the pad where locate the IC power supply pin.

To control the standard mode EMI, the power plane will help decouple and have a sufficiently low inductance, which must be a well-designed power layer pairing. Some people may ask, to what extent is it useful? The answer to the problem depends on the stratification of the power supply, the material between the layers, and the operating frequency (i.e., the function of IC rise time). Typically, the spacing of the power supply is six mils, and the interlayer is FR4 material, the equivalent capacitance per square inch of the power supply layer is about 75pF. The smaller the interlayer spacing, the larger the capacitance.

There are not many devices with a rise time of 100 to 300 ps, but devices with high rise times in the range of 100 to 300ps will have a high percentage according to the current IC development speed. For circuits with a rise time of 100 to 300 ps, the three mil layer spacing will no longer apply to most applications. At that time, it is necessary to use layer spacing of less than 1mil layered technology, and with a high dielectric constant material instead of FR4 dielectric material. Now, ceramic and pottery plastic can meet the design requirements of the 100 to 300ps rise time circuit.

Although new materials and new methods may be used in the future, for today’s standard 1 to 3 ns rise time circuits, the 3 to 6 mil layer spacing and FR4 dielectric material are usually sufficient to handle high-end harmonics and make the transient signal low enough, Common mode EMI can drop very low. The PCB stacking design example presented in this paper will assume a layer spacing of 3 to 6 mils.

Electromagnetic Shielding

From the signal alignment, a good stratification strategy should put all the signal lines on a layer or layers, these layers next to the power layer or ground plane. For power, a good stratification strategy should be the power layer and the ground layer adjacent to the power layer and the ground layer as small as possible, which is what we talk about the “layered” strategy.

PCB Stacking

What kind of stacking strategy helps to shield and suppress EMI? The following layered stacking scheme assumes that the supply current flows on a single layer and that a single voltage or multiple voltages are distributed across different parts of the same layer. The situation of the multi-power layer is discussed later.

  4 Layers

There are several potential problems with 4-layer board design. First, the traditional thickness of 62mil four-layer board, even if the signal layer in the outer layer, power and ground layer in the inner layer, the power supply layer and the ground layer spacing is still too large.

If the cost requirement is the first, consider the following two traditional 4-layer alternatives. Both of these solutions improve EMI suppression performance, but only for applications where the board component density is low enough, and there is sufficient area around the component (placing the required power cladding layer).

The first is the preferred solution, the outer layers of the PCB are strata, and the middle two are signal/power layers. The power supply on the signal layer is routed with a wide line, which makes the path impedance of the supply current low, and the impedance of the signal microstrip path is low. From the EMI control point of view, this is the best existing 4-layer PCB structure. The second program of the outer layer of power and ground, the middle two layers of the signal. The solution is less important than the traditional 4-layer board, and the interlayer impedance is as bad as the traditional 4-layer board.

If you want to control the trace impedance, the stacking solution should be carefully placed in the power supply and ground bridge below the copper island. In addition, the copper or the copper on the power source or formation should be interconnected as much as possible to ensure DC and low-frequency connectivity.

Six layers

If the component density on the 4-layer PCB board is relatively large, it is preferable to use a 6-layer circuit board. However, some of the stacking schemes in the 6-layer PCB board design are not good enough for the shielding of the electromagnetic field, which has little effect on the reduction of the transient signal of the power supply bus. Two examples are discussed below.

The first example of the power and ground were placed on the 2nd and 5th, due to the power supply copper resistance is high, the control of common mode EMI radiation is very negative. However, from the signal impedance control point of view, this method is correct.

The second example places the power supply and ground on the 3rd and 4th layers, and this design solves the problem of the copper cladding of the power supply. Since the electromagnetic shielding performance of the first and sixth layers is poor, the differential mode EMI increases. This design solves the differential mode EMI problem if the number of signal lines on both outer layers is the least and the trace length is very short (less than 1/20 of the highest harmonic wavelength of the signal). The suppression of the differential mode EMI is particularly good by filling the non-element and non-traces of the outer layer with copper and grounding the copper area (at every 1/20 wavelength interval). As mentioned earlier, the copper area is to be connected to the internal ground plane.

General high-performance 6-layer board design generally the first and sixth layer of cloth for the formation, the third and fourth floor to take power and ground. Since the dual layer of the microstrip signal line is centered between the power supply layer and the ground layer, the EMI suppression capability is excellent. The drawback of this design is that there are only two layers of the wiring layer. As mentioned earlier, if the outer traces are short and copper is routed in the non-traced area, the same stack can also be achieved with a conventional 6-layer board.

Another 6-layer board layout for the signal, ground, signal, power, ground, signal, which can achieve advanced signal integrity design required environment. The signal layer is adjacent to the ground plane, and the power supply layer and the ground plane are paired. The downside is that the layers of the stack are unbalanced.

This usually causes trouble in PCB manufacturing. The solution to the problem is to fill all the blank areas of the third layer of copper, fill copper if the third layer of copper density close to the power layer or ground layer, the board can not be strictly counted as a structural balance of the circuit board The The copper-filled area must be connected to the power supply or grounded. The distance between the connecting vias is still 1/20 wavelength, not necessarily connected everywhere, but ideally should be connected.

10 Layers

Since the insulation isolation layer between the multilayer boards is very thin, the impedance between the circuit board layers of the 10 or 12 layers is very low, and excellent signal integrity is expected to be achieved as long as there is no problem with delamination and stacking. According to the thickness of 62mil manufacturing 12-layer board, the more difficult to be able to process 12-layer board manufacturers are not many.

Since there is always an insulating layer between the signal layer and the circuit layer, it is not optimal to allocate the middle 6-layer signal line in the 10-layer board design. In addition, it is important that the signal layer and the circuit layer are adjacent, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, ground, signal.

This design provides a good path for the signal current and its loop current. The proper routing strategy is that the first layer is traced along the X direction, the third layer is traced along the Y direction, the fourth layer is traced along the X direction, and so on. Intuitive to see the line, the first layer one and the third layer is a pair of hierarchical combination, the fourth and seventh layer is a pair of layered combination, 8th and 10th layer is the last pair of layered combination. When the direction of the alignment needs to be changed, the signal lines on layer 1 should be changed by “via” to layer 3. In fact, it may not always be done, but as a design concept or to try to comply.

Similarly, when the signal alignment direction changes, it should be through the hole from the 8th and 10th layers or from the 4th to 7th floor. This wiring ensures that the coupling between the forward path and the loop of the signal is tightest. For example, if the message is routed on layer one and the circle is on layer 2. Only on layer 2, the sign on sheet one is transferred to layer three even by “vias” The circuit is still on the second floor, thus maintaining low inductance, broad capacitance characteristics, and excellent electromagnetic shielding performance.

If the actual alignment is not the case, how do? Such as the first layer of the signal line through the hole to the 10th layer, then the loop signal had to find from the 9th-floor ground plane, loop current to find the nearest ground vias (such as resistors or capacitors and other components of the ground pin) The If you happen to have such a hole in the vicinity, it is fortunate. If there are no such vias available, the inductance will become more abundant, and the capacitance will be reduced, EMI will increase.

When the signal line must pass through the hole from the current pair of wiring layer to the other wiring layer, should be placed near the hole in the ground through the hole, so that the circuit signal can be successfully returned to the appropriate ground plane. For Layer 4 and Layer 7 hierarchical combinations, the signal loop will return from the power plane or ground plane (i.e., layer five or layer 6) because of the capacitive coupling between the power supply layer and the ground plane is excellent and the signal is easy to transmit.

Multi-power Layer Design

If the two power supply layers of the same voltage source need to output high current, the circuit board should be fabricated into two power supply layers and ground planes. In this case, an insulating layer is placed between each pair of the power supply layer and the ground layer. This gives us the desired equalization of the current of two pairs of impedance equal to the power bus. If the stacking of the power supply layer causes the impedance to be unequal, the shunt is not uniform, the transient voltage will be much larger, and the EMI will increase dramatically.

If there are multiple values of different supply voltages on the board, numerous power planes are required accordingly, keeping in mind the separate power supply layers and ground layers for various power sources. In both cases, make sure that the pairing power supply layer and the ground plane are at the location of the circuit board, bearing in mind the manufacturer’s requirements for the balanced structure.

To Sum Up

The discussion of circuit board delamination and stacking is limited to the fact that most engineers design circuit boards with a conventional printed circuit board with a thickness of 62 mils without blind holes or buried vias. Thickness difference is too vast for the circuit board, and the proposed stratification scheme may not be ideal. Also, the blind hole or hidden hole, circuit board processing process is different from the stratification method is not applicable.

The thickness of the circuit board design, via the process and the number of layers of the circuit board, is not the key to solve the problem. The great layered stack is to ensure the bypass and decoupling of the power supply bus so that the transient voltage on the power supply layer or ground layer is the smallest And the signal and power of the electromagnetic field shielding the key. Ideally, there should be an insulation barrier between the signal trace layer and its return ground layer, and the paired layer spacing (or one or more) should be as small as possible. According to these basic concepts and principles, it can be designed to meet the design requirements of the circuit board. Now, IC’s rise time is short and will be shorter, the technology discussed in this paper to solve the problem of EMI shielding is essential

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